1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Increasingly higher degrees of integration continue to be achieved in semiconductor integrated circuits, especially integrated circuits that use MOS transistors. With the increase in the degree of integration, MOS transistors used in integrated circuits have scaled down to the nanometer order. As the miniaturization of the MOS transistors proceeds, it is becoming increasingly difficult to suppress leak current and to reduce the area occupied by the circuits while maintaining a required amount of current. In order to address these challenges, surrounding gate transistors (referred to as “SGTs” hereinafter) in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer have been proposed (for example, refer to Japanese Unexamined Patent Application Nos. 2-71556, 2-188966, and 3-145761).
According to a conventional method for producing SGTs, a contact hole in an upper portion of a silicon pillar is formed separately from a contact hole in a lower portion of the silicon pillar and on a planar silicon layer since the depths of these contacts are different from each other (for example, refer to Japanese Unexamined Patent Application Publication No. 2012-004244). Since the contact holes are formed separately, the number of steps is increased.
While the contact hole in the upper portion of a silicon pillar is formed separately from the contact hole in the lower portion of the silicon pillar and on the planar silicon layer, excessively etching the contact hole in the upper portion of the silicon pillar may result in etching of a gate electrode. If etching is insufficient, there is a possibility that the silicon pillar upper portion is insulated from the contact.
Since the contact hole in the lower portion of the silicon pillar and on the planar silicon layer is deep, it is difficult to fill the contact hole. Moreover, it is difficult to form a deep contact hole.
According to a conventional method for producing SGTs, a silicon pillar in which a nitride film hard mask is formed to have a pillar shape is formed, a diffusion layer is formed in a lower portion of the silicon pillar, a gate material is then deposited, planarized and etched back, and an insulating film side wall is formed on a side wall of the silicon pillar and the nitride film hard mask. Then a resist pattern for a gate line is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed in an upper portion of the silicon pillar (for example, refer to Japanese Unexamined Patent Application No. 2009-182317).
In this method, in the cases where intervals between silicon pillars are narrow and a thick gate material must be deposited between the silicon pillars, holes called voids are sometimes formed between the silicon pillars. Formation of voids leads to formation of holes in the gate material after etch back. When an insulating film is deposited to form the insulating film side wall, the insulating film is deposited in the voids. Accordingly, it becomes more difficult to work with the gate material.
To address this, a proposal has been made (for example, refer to B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. D. Lo, and D. L. Kwong, “Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET”, IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp. 791-794) in which a gate oxide film is formed after formation of a silicon pillar, a thin polysilicon is deposited, a resist covering an upper portion of the silicon pillar and for forming a gate line is then formed, a gate line is etched, an oxide film is then thickly deposited, the upper portion of the silicon pillar is exposed, the thin polysilicon on the upper portion of the silicon pillar is removed, and the thick oxide film is removed by wet etching.
However, a method in which a metal is used in the gate electrode is not described. Moreover, a resist covering an upper portion of the silicon pillar and for forming a gate line must be formed and the upper portion of the silicon pillar must be covered; thus, this method is not a self-aligned process.
In order to decrease the parasitic capacitance between the gate line and the substrate, a conventional MOS transistor uses a first insulating film. For example, in a FINFET (High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme, IEDM 2010 CC. Wu, et. al, 27.1.1-27.1.4), a first insulating film is formed around one fin-shaped semiconductor layer and is etched back to expose the fin-shaped semiconductor layer so as to decrease the parasitic capacitance between the gate line and the substrate. Thus, the first insulating film must be used to decrease the parasitic capacitance between the gate line and the substrate in the SGT also. Since a SGT includes a pillar-shaped semiconductor layer in addition to a fin-shaped semiconductor layer, adjustment must be made for forming the pillar-shaped semiconductor layer.